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pv200:vyuka

PV200 - Introduction to hardware description languages

  • Room A415 - monday - 16:00 – 18:00
  • xmatej@fi.muni.cz

HW & SW

Content

  • Programmable structures fundamentals
  • Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
  • Designing in Verilog – combinational primitives, sequential circuits, state machine design
  • FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice
  • Prefabricated components – IP cores, Megafunctions
  • Interfaces & Peripherals – RS232, LCD, keyboard
  • Introduction to VHDL
  • Sofcore computing – introduction to NIOS2 processor system

1. lecture

2. lecture

  • Altera Quartus + schematic
  • Simulation tool - University program
  • Full 1-bit adder - 2 half-adder → 2×2-bit adder

3. lecture

4. lecture

5. lecture

  • Ex. 1 - PWM generator - all LEDs
  • Ex. 2 - change PWM duty cycle via BTN1 and BTN2 - 0 to 100 %
  • Ex. 3 - Divider 50:50
  • Ex. 4 - Knight rider (3 LEDS - 100%; 50%; 20%; 10%) - homework
  • HEX counter nios_DE2_demo
  • HEX counter hex_7seg

6. lecture

  • FSM (Finite State Machine)
    • Mealy
    • Moore
    • Save FSM
  • Exercise:
    • 10 s coutdown with 7-segment (down counter → 7-segment decoder)
    • on the end - blinking RED LEDs
    • reset - BTN1
    • ADD: set initial value using hold the first button, then start pressing the second button

7. lecture

8. lecture

Nios II/f

  • The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
    • Separate instruction and data caches (512 B to 64 kB)
    • Optional MMU or MPU
    • Access to up to 2 GB of external address space
    • Optional tightly coupled memory for instructions and data
    • Six-stage pipeline to achieve maximum DMIPS/MHz
    • Single-cycle hardware multiply and barrel shifter
    • Optional hardware divide option
    • Dynamic branch prediction
    • Up to 256 custom instructions and unlimited hardware accelerators
    • JTAG debug module
    • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

Project

  • Dlhopolcek - Audio efekty + NIOS II
  • Novacik - Snake (+ NIOS II)
  • Paral - Snake + PS2 keyboard + NIOS II
  • Barna - MD5
  • Obetko - IRDA - copy of remotre control
  • van Hoef - ethernet remote control

X. lecture

X. lecture

X. lecture

X. lecture

  • simulation tools (Modelsim)
  • logic analyser

Projects

  • 16-bit softcore CPU - Salvet
  • Delta-deciballity solder - Pastva
  • Serial communication + LCD - Deniz
  • LCD screen + serial communication as graphical terminal - Sedat
  • audio filter - Stanka
Project example
  • MD5 cracker
  • video filters
  • audio filters
  • ethernet analyzer
  • graphical efects on LCD screen (fractal…)
  • PS2 + LCD
  • logic analyser
  • snake, pacman…
  • GPS receiver
  • IRDA communication
pv200/vyuka.txt · Last modified: 2017/12/04 16:52 by root