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pv200:vyuka

PV200 - Introduction to hardware description languages

  • Room A415 - monday - 16:00 – 18:00
  • xmatej@fi.muni.cz

HW & SW

Content

  • Programmable structures fundamentals
  • Verilog HDL – concepts, basic syntax, abstraction levels, design hierarchy.
  • Designing in Verilog – combinational primitives, sequential circuits, state machine design
  • FPGA devices – capabilities, limitations, programming. Advanced features in Verilog, best practice
  • Prefabricated components – IP cores, Megafunctions
  • Interfaces & Peripherals – RS232, LCD, keyboard
  • Introduction to VHDL
  • Sofcore computing – introduction to NIOS2 processor system

1. lecture

2. lecture

  • Altera Quartus + schematic
  • Simulation tool
  • Full 1-bit adder - 2 half-adder

3. lecture

4. lecture

  • Verilog practise
  • Ex. 1: Divider 50:50
  • Ex. 2: HEX counter 2-digits (coder) - DE2-full assigments
  • HEX counter nios_DE2_demo
  • HEX counter hex_7seg

5. lecture

  • Ex.1 - PWM generator - all LEDs
  • EX.2 - change PWM duty cycle via BTN1 and BTN2 - 0 to 100 %

6. lecture

  • reset - SYNCH/ASYNCH
  • EX.1 - countdown:
    • divide clock signal
    • coutdown with 7-segment (down counter → 7-segment decoder)
    • on the end - blinking RED LEDs
    • reset - BTN1
    • ADD: set initial value using hold the first button, then start pressing the second button

7. lecture

8. lecture

9. lecture

10. lecture

  • simulation tools (Modelsim)
  • logic analyser

Projects

  • 16-bit softcore CPU - Salvet
  • Delta-deciballity solder - Pastva
  • Serial communication + LCD - Deniz
  • LCD screen + serial communication as graphical terminal - Sedat
  • audio filter - Stanka
Project example
  • MD5 cracker
  • video filters
  • audio filters
  • ethernet analyzer
  • graphical efects on LCD screen (fractal…)
  • PS2 + LCD
  • logic analyser
  • snake, pacman…
  • GPS receiver
  • IRDA communication
pv200/vyuka.txt · Last modified: 2017/09/18 14:07 by root